Key Responsibilities：
1. Be part of IO IP team, joining IP architecture work to define host controller IP structure for next generation of leading-edge super high-speed IO. Establishes and maintains high speed IO technological leadership position;
2. Defines and develops micro-architecture for host controller design, based on architectural requirement for next generation IO. Leads RTL code development for IP blocks in Verilog HDL and make sure functional correct and reusable for different product lines;
3. Is responsible for projects or processes of significant strategic or commercial importance and for project/program results;
4. Deals with problems requiring cutting edge approaches and champions innovation across the organization;
5. Provides consultative direction with senior management;
6. Makes technical decisions that have a significant impact on product families, go to market strategies and customer satisfaction;
7. Coaches and mentors experienced staff;
8. Represents IO team to the outside technical community, partners and vendors.
Skills and Experiences：
1. MS degree of EE or CS, with minimum 12 years’ experience;
2. Specialized knowledge of USB 3.0/3.1/3.2 or Thunderbolt in protocol and link layers is preferred. Specialized knowledge of PCIE or AMBA is a plus;
3. Expert of IP micro-architecture and Verilog RTL design on large size digital IP;
4. Considered technical leader across project and departmental boundaries and has a proven track record for sustained innovation;
5. Fluent English on talking, presentation and writing documents;
6. Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager;
7. Can solve complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation.
