KEY RESPONSIBILITIES： 1. New feature effort scoping; 2. Feature test plan and DRVR writer, split down the tasks and assign to engineers; 3. Attend global conference call for verification strategy alignment, status sync up etc. with global team; 4. Drive and monitor other engineers to accomplish tasks on schedule; 5. Sign-off owned features/projects; 6. Ramp-up new hires 7. Short term global travel if needed
PREFERRED EXPERIENCE： 1. Global company working experience, fluent oral English 2. Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred. 3. Good knowledge of UVM/Verilog/System C/SystemVerilog. 4. Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA), insights into random techniques. 5. Experience of verification lead is an asset; 6. Experience of verification planning is an asset; 7. Knowledge of Virtualization is an asset; 8. Strong scripting languages (Perl, C Shell, Makefile, …) experience; 9. Strong collaboration skill set.
ACADEMIC CREDENTIALS： 1. MSEE within 5-10 years, or BSEE within 8-12 years’ experience in digital ASIC/SOC design verification.
